The present invention relates generally to semiconductor processing technology, and more particularly to a metal-oxide-semiconductor (MOS) device with a high voltage isolation structure.
While recent development of MOS transistors has predominantly focused on very large scale integration (VLSI) technology, radio frequency (RF) MOS transistors are still commonly used for high power RF applications. The differences between the RF MOS transistors and VLSI devices are that the former have a larger channel length, greater junction depths and thicker gate oxides, as required to sustain the high power needed for most RF applications. Recent RF applications demand even more power. Most high power RF applications operate at supply voltages ranging from 20 to 50 volts.
There are two basic types of RF MOS transistors: the double-diffused MOS (DMOS) transistors, and the laterally-diffused MOS (LDMOS) transistors. While the two types of RF MOS transistors are different structurally with their unique behaviors, the transistors for both types are composed of a source, a gate, and a drain, with a substrate shorted to the source and a voltage applied on the gate for controlling the current flow between the drain and the source.
An LDMOS transistor is constructed in some occasions as a symmetric power MOS transistor. In a conventional method used for forming a high voltage isolation structure for a symmetric LDPMOS transistor, an N-type buried layer (NBL) is implemented between an epitaxial (EPI) layer and the substrate of the transistor. The EPI layer is required to be of a certain thickness for properly isolating the wells of the transistor from the substrate. In fact, as the operation voltage of the transistors becomes higher, the EPI layer needs to be thicker. However, the transistor may fail when the EPI layer is too thick. An improperly thick EPI layer can create a leakage current path between the source/drain regions of the transistor, which can cause the transistor to malfunction.
Desirable in the art of semiconductor processing technology are methods for forming a MOS transistor with a high voltage isolation structure for eliminating the current leakage issue induced by an improperly thick EPI layer.